`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer: 
// 
// Create Date:    23:30:13 10/24/2012 
// Design Name: 
// Module Name:    DN_SAMPLE_UNIT 
// Project Name: 
// Target Devices: 
// Tool versions: 
// Description: 
//
// Dependencies: 
//
// Revision: 
// Revision 0.01 - File Created
// Additional Comments: 
//
//////////////////////////////////////////////////////////////////////////////////
module DN_SAMPLE_UNIT #(parameter LOG_RATE=3, RATE=8, WIDTH=16)
(
	 input clk,
	 input rst,
    input signed [WIDTH-1:0] data_in,
    output reg signed[WIDTH-1:0] data_out
    );
	 
	 reg[LOG_RATE-1:0] count;
	 
	 always @(posedge clk or negedge rst)
		if(!rst)
		begin
			count <= 0;
			data_out <= 0;
		end
		else
			if(count == RATE-1)
			begin
				count <= 0;
				data_out <= data_in;
			end
			else
			begin
				count <= count + 1;
				data_out <= data_out;
			end


endmodule
